Over the last few years digital logic circuits have been increasing in speed and decreasing in size. As more digital circuitry is packed into a device, power consumption becomes an increasingly important issue. For example, cell phones, Personal Digital Assistants (PDAs), cameras, and so forth, rely on batteries, and minimizing power consumption is a major design goal. As these digital logic circuits include many flip-flops, reducing power usage by these flip-flops, reduces overall power consumption.
FIG. 1 is a schematic circuit diagram of a typical prior art fast D type flip-flop 110, a Hybrid Latch Flip-Flop (HLFF). The data input is D 112, the clock signal CLK0 114, and the output Q 116. The two inverters 117 and 118 are a “keeper” circuit which maintains the value of Q 116. CLK3 126 is the clock signal CLK0 114 inverted and delayed by the three inverters 120, 122, and 124. A transparency window for the HLFF is given by the propagation delay of the three inverters, 120, 122, and 124, connecting CLK0 114 to CLK3 126. The first stage 130 of the HLFF generates a high-to-low transition on node X 150 in the transparency window when the input D 112 signal is high. The first stage 130 is formed by a static CMOS 3-input NAND gate. The second stage 140 captures the transition on node X 150 generated by the first stage 130 and produces output Q 116. When the input D 112 is at the low logic level, the high-to-low transition on node X 150 does not appear.
FIG. 2 is a timing diagram for the prior art HLFF schematic circuit diagram of FIG. 1 showing a glitch in the output and unnecessary power consumption. The timing diagram shows the clock signals CLK0 210 and CLK3 212 representing the CLK0 114 and CLK3 126 in FIG. 1, respectively. A transparency window is shown by the time interval 222, which represents the three inverter delay. D 214, X 216, and Q 218 show the signals for D 112, node X 150, and Q 116 in FIG. 1 respectively. For example, an undesirable glitch occurs in a clock cycle 229, when Q 218 was set to high with D 214 equal to high at a previous clock cycle 228. At CLK0 transition 230 (a low logic level (L) to a high logic level (H)), D 214 is still H 232. During the nonzero time required for the evaluation of the first stage 130 (to set node X 150 to L), the second stage output Q 218 is pulled low, i.e., transition 234, since X 216 is H and the transparency window is open. After the first stage 130 changes X 216 to L, i.e., transition 236, the second stage 140 pulls Q 218 back up to H, i.e., transition 240. Hence a glitch in Q 218 occurs, when Q 218 should not change at all since D 214 is still one. The glitch is not only a potential hazard condition, but also consumes power unnecessarily.
The H to L transition 236 and L to H transition 244 of X 216 in FIG. 2 illustrates an additional power consumption problem, because the HLFF circuit consumes internal power even when the input is quiet (D=Q=H). As illustrated, there is an unconditional capture of the data level in the transparency window when the data is at a constant high level, i.e., when both input D and output Q are at H. In other words, X 216, in this constant high level case, always transitions from H to L following a positive clock edge, e.g., clock edge 230. However, this does not have any functionality since it can only set the output Q 116 to H, and the level the output Q 116 is already at H. Thus, the HLFF has a both hazard condition and a power consumption problem.
Another conventional flip-flop design is the Conditional Capture Flip-Flop (CCFF), which reduces the power consumption problem of the HLFF by inhibiting internal transitions if they are not going to be used to change the state of the flip-flop. FIG. 3 shows a single-ended version of the CCFF. In FIG. 3 a D type flip-flop is shown with input D 312, output Q 330, and Clock CLK0 314. The inverters 332 and 334 are for the keeper circuit for the output Q 330. CLK3 316 is the clock inverted and delayed by the three inverters 320, 322, and 324. When the input clock CLK0 314 is at L, the node X 315 is pre-charged (H). When the clock makes a L to H transition, the input D 312 is H, and the output Q 330 is L, the node X 315 determination is controlled by the pull-down nMOS path (Mn1 350, Mn2 352, and Mn3 354) of the first stage 355, which is open only in the transparency window (delay of two inverters, 320 and 322 and a NOR gate 340). The low level of node X 315 changes the output Q 330 from L to H. If there was a change of D 312 in or before the transparency window, the change of input D 312 from L to H is governed by the delay of the first stage 355 to set node X 315, because once node X 315 is L, Mp4 362 will pull Q 330 to H. The NOR gate 340 and Mp3 363 disables the evaluation of the first stage 355, if the low level of X is not going to be used to change the output level, i.e., when D 312 and Q 330 are already H. If the node X 315 remains high due to a L level on input D 312, the output Q 330 is set from H to L by the transistors Mn4 364, Mn5 366 and Mn6 368. If there was a change of D 312 in the transparency window, the change of input D 312 from H to L is governed by the delay of the inverter 360 to set Mn5 366.
While the CCFF typically has lower power consumption than the HLFF, there are several problems. First, it has a significantly higher delay time than the HLFF. This is due in part to the difference in the implementations of the conditional transparency window for L to H and H to L input D 312 transitions (assuming changes in the output Q 330). In effect, this reduces set-up time for the H to L transition at the input, since the transition has to propagate through the inverter 360 in order to be captured in the transparency window. In contrast, the L to H transition has a longer set-up time (by one inverter delay), because it may occur substantially in the transparency window, since it is captured from node X 315 out of the first stage 355. The result is a mismatch in set-up times for the two transitions (L to H and H to L) and consequently poor timing characteristics.
Another problem of the increased set-up time for the H to L transition, occurs when a heavy load is at the output Q 330 of the CCFF. Since the H to L transition of Q is allowed only in the transparency window, the arrival of the D input transition (H to L) may need to occur before the beginning of the transparency window in order to ensure proper discharge of Q 330 before the transparency window closes.
There is also a problem of power consumption in the output keepers of the HLFF and CCFF above (inverters 117 and 118 of FIG. 1 and inverters 332 and 334 of FIG. 3). The keeper is-used to hold the value of a dynamic node, e.g., Q, that would otherwise be in high impedance and thus sensitive to leakage current effects and noise, especially in low-power applications where clock gating techniques are typically employed. The problem is that in order to change the value of the output Q, the keeper has to be overpowered, which increases power consumption.
Therefore with the problems of hazard and power consumption with the HLFF and increased delay and set-up time problems with the CCFF, there is a need for an improved flip-flop with less problems, including improved power consumption. In addition there is a need for an improved flip-flop with the low delay advantage of the HLFF without the associated glitch and power consumption problems.